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w942508ch 8m 4 banks 8 bit ddr sdram publication release date: may 21, 2003 - 1 - revision a3 table of contents- 1. general description .................................................................................................. 3 2. features ....................................................................................................................... ... 3 3. key parameters ............................................................................................................ 4 4. pin configuration ........................................................................................................ 5 5. pin description.............................................................................................................. 6 6. block diagram ............................................................................................................... 7 7. electrical characteristics .................................................................................... 8 7.1 absolute maximum ratings ................................................................................................. 8 7.2 recommended dc operating conditions............................................................................ 8 7.3 capacitance .................................................................................................................... ..... 9 7.4 leakage and output buffer characteristics ......................................................................... 9 7.5 dc characteristics ............................................................................................................. 10 7.6 ac characteristics and operating condition ..................................................................... 11 7.7 ac test conditions ............................................................................................................ 1 3 8. operation mode ................................................................................................................. 15 8.1 simplified truth table ........................................................................................................ 1 5 8.2 function truth table .......................................................................................................... 1 6 8.3 function truth table for cke ............................................................................................ 19 8.4 simplified state diagram.................................................................................................... 20 9. functional description........................................................................................... 21 9.1 power up sequence .......................................................................................................... 21 9.2 command function............................................................................................................ 21 9.3 read operation................................................................................................................. .24 9.4 write operation ................................................................................................................ .. 24 9.5 precharge...................................................................................................................... ..... 24 9.6 burst termination.............................................................................................................. .25 9.7 refresh operation.............................................................................................................. 25 9.8 power down mode............................................................................................................. 25 9.9 mode register operation ................................................................................................... 25 10. timing wave forms ............................................................................................................. 29 10.1 command input timing...................................................................................................... 29 10.2 timing of the clk signals.................................................................................................. 29 10.3 read timing (burst length = 4) ......................................................................................... 30 10.4 write timing (burst length = 4) ......................................................................................... 31 10.5 dm, data mask (w942508ch/w942504ch) ................................................................. 32
w942508ch - 2 - 10.6 dm, data mask (w942516ch)....................................................................................... 32 10.7 mode register set (mrs) timing ...................................................................................... 33 10.8 extend mode register set (emrs) timing........................................................................ 34 10.9 auto precharge timing (read cycle, cl = 2).................................................................... 35 10.10 auto precharge timing (write cycle)................................................................................. 37 10.11 read interrupted by read (cl = 2, bl = 2, 4, 8) ............................................................... 38 10.12 burst read stop (bl = 8) ................................................................................................... 38 10.13 read interrupted by write & bst (bl = 8)......................................................................... 39 10.14 read interrupted by precharge (bl = 8) ............................................................................ 39 10.15 write interrupted by write (bl = 2, 4, 8) ............................................................................ 40 10.16 write interrupted by read (cl = 2, bl = 8) ....................................................................... 40 10.17 write interrupted by read (cl = 2.5, bl = 4) .................................................................... 41 10.18 write interrupted by precharge (bl = 8) ............................................................................ 41 10.19 2 bank interleave read operation (cl = 2, bl = 2) .......................................................... 42 10.20 2 bank interleave read operation (cl = 2, bl = 4) .......................................................... 42 10.21 4 bank interleave read operation (cl = 2, bl = 2) .......................................................... 43 10.22 4 bank interleave read operation (cl = 2, bl = 4) .......................................................... 43 10.23 auto refresh cycle ............................................................................................................ 4 4 10.24 active power down mode entry and exit timing............................................................... 44 10.25 precharged power down mode entry and exit timing ...................................................... 44 10.26 self refresh entry and exit timing .................................................................................... 45 11. package dime nsion ........................................................................................................... 46 11.1 tsop 66l ? 400 mil ............................................................................................................ 4 6 12. revision histor y ............................................................................................................... .47
w942508ch publication release date: may 21, 2003 - 3 - revision a3 1. general description w942508ch is a cmos double data rate synchronous dynamic random access memory (ddr sdram), organized as 8,388,608 words 4 banks 8 bits. using pipelined architecture and 0.13 m process technology, w942508ch delivers a data bandwidth of up to 400m words per second (-5). to fully comply with the personal computer industri al standard, w942508ch is sorted into four speed grades: -5, -6, -7, -75 the -5 is compliant to the 200mhz/cl2.5 & cl3 specification, the -6 is compliant to the 166mhz/cl2.5 sp ecification, the -7 is comp liant to the 143mhz/cl2.5 or ddr266/cl2 specification, the -75 is comp liant to the ddr266/cl2.5 specification. all inputs reference to the posit ive edge of clk (except for dq, dm, and cke). the timing reference point for the differential clock is when the clk and clk signals cross during a transition. and write and read data are synschronized with the both edges of dqs (data strobe). by having a programmable mode r egister, the system can change burst length, latency cycle, interleave or sequential burst to maximize its per formance. w942508ch is ideal for main memory in high performance applications. 2. features ? 2.5v 0.2v power supply for ddr266 ? 2.5v 0.2v power supply for ddr333 ? 2.6v 0.1v power supply for ddr400 ? up to 200 mhz clock frequency ? double data rate architecture; two data transfers per clock cycle ? differential clock inputs (clk and clk ) ? dqs is edge-aligned with data for read; center-aligned with data for write ? cas latency: 2, 2.5 and 3 ? burst length: 2, 4 and 8 ? auto refresh and self refresh ? precharged power down and active power down ? write data mask ? write latency = 1 ? 8k refresh cycles / 64 ms ? interface: sstl-2 ? packaged in tsop ii 66-pin, 400 x 875mil, 0.65mm pin pitch
w942508ch - 4 - 3. key parameters symbol description min./max. -7 -75 cl = 2 min. 7.5 ns 8 ns t ck clock cycle time cl = 2.5 min. 7 ns 7.5 ns t ras active to precharge command period min. 45 ns 45 ns t rc active to ref/active command period min. 65 ns 65 ns i dd1 operation current (single bank) max. 120 ma 120 ma i dd4 burst operation current max. 165 ma 155 ma i dd6 self-refresh current max. 3 ma 3 ma symbol description min./max. -5 -6 cl = 2.5 min. 5 ns 6 ns t ck clock cycle time cl = 3 min. 5 ns 6 ns t ras active to precharge command period min. 40 ns 42 ns t rc active to ref/active command period min. 55 ns 60 ns i dd1 operation current (single bank) max. 120 ma 120 ma i dd4 burst operation current max. 165 ma 165 ma i dd6 self-refresh current max. 3 ma 3 ma
w942508ch publication release date: may 21, 2003 - 5 - revision a3 4. pin configuration v ss dq7 v ss q nc2 dq6 v dd q nc2 dq5 v ss q nc2 dq4 v dd q nc2 v ss nc1 dqs clk cke a11 a9 a8 a7 a6 a5 a4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v dd dq0 v dd q nc2 dq1 v ss q nc2 dq2 v dd q nc2 dq3 v ss q nc2 nc1 v dd q bs0 bs1 a10/ap a0 a1 a2 a3 cs ras cas we 28 29 30 31 32 33 39 38 37 36 35 34 v dd nc2 nc1 nc2 nc1 v dd nc1 v ss q nc1 a12 nc1 clk dm v ref
w942508ch - 6 - 5. pin description pin number pin name function description 28 ? 32, 35 ? 42 a0 ? a12 address multiplexed pins for row and column address. row address: a0 ? a12. column address: a0 ? a9. (a10 is used for auto precharge) 26, 27 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during column address latch time. 2, 5, 8, 11, 56, 59, 62, 65 dq0 ? dq7 data input/ output the dq0 ? dq7 input and output data are synchronized with both edges of dqs. 51 dqs data strobe dqs is bi-directional signal. dqs is input signal during write operation and output signal duri ng read operation. it is edge- aligned with read data, cent er-aligned with write data. 24 cs chip select disable or enable the command decoder. when command decoder is disabled, new co mmand is ignored and previous operation continues. 23, 22, 21 ras , cas , we command inputs command inputs (along with cs ) define the command being entered. 47 dm write mask when dm is asserted " high " in burst write, the input data is masked. dm is synchroniz ed with both edges of dqs. 45, 46 clk, clk differential clock inputs all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of clk . 44 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 49 v ref reference voltage v ref is reference voltage for inputs. 1, 18, 33 v dd power (+2.5) power for logic circuit inside ddr sdram. 34, 48, 66 v ss ground ground for logic circuit inside ddr sdram. 3, 9, 15, 55, 61 v ddq power (+2.5v) for i/o buffer separated power from v dd , used for output buffer, to improve noise. 6, 12, 52, 58, 64 v ssq ground for i/o buffer separated ground from v ss , used for output buffer, to improve noise. 4, 7, 10, 13, 14, 16, 17, 19, 20, 25, 43, 50, 53, 54, 57, 60, 63 nc1, nc2 no connection no connection
w942508ch publication release date: may 21, 2003 - 7 - revision a3 6. block diagram dqs cke a10 dll clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 8912 * 1024 * 8 row decoder row decoder row decoder row decoder a0 a9 a11 a12 ba0 ba1 cs ras cas we clk clk dm dq0 dq7 prefetch register
w942508ch - 8 - 7. electrical characteristics 7.1 absolute maximum ratings parameter symbol rating unit input/output voltage v in , v out -0.3 ? v ddq +0.3 v power supply voltage v dd , v ddq -0.3 ? 3.6 v operating temperature t opr 0 ? 70 c storage temperature t stg -55 ? 150 c soldering temperature (10s) t solder 260 c power dissipation p d 1 w short circuit output current i out 50 ma note: exposure to conditions beyond those lis ted under absolute maximum ratings may adversely affect the life and reliability of the device. 7.2 recommended dc operating conditions (t a = 0 to 70 c) symbol parameter min. typ. max. unit notes v dd power supply voltage 2.3 2.5 2.7 v 2 v ddq power supply voltage (for i/o buffer) 2.3 2.5 v dd v 2 v ref input reference voltage 0.49 x v ddq 0.50 x v ddq 0.51 x v ddq v 2, 3 v tt termination voltage (system) v ref -0.04 vref v ref +0.04 v 2, 8 v ih (dc) input high voltage (dc) v ref +0.15 - v ddq +0.3 v 2 v il (dc) input low voltage (dc) -0.3 - v ref -0.15 v 2 v ick (dc) differential clock dc input voltage -0.3 - v ddq +0.3 v 15 v id (dc) input differential voltage. clk and clk inputs (dc) 0.36 - v ddq +0.6 v 13, 15 v ih (ac) input high voltage (ac) v ref +0.31 - - v 2 v il (ac) input low voltage (ac) - - v ref -0.31 v 2 v id (ac) input differential voltage. clk and clk inputs (ac) 0.7 - v ddq +0.6 v 13, 15 v x (ac) differential ac input cross point voltage v ddq /2 -0.2 - v ddq /2 +0.2 v 12, 15 v iso (ac) differential clock ac middle point v ddq /2 -0.2 - v ddq /2 +0.2 v 14, 15 notes: undershoot limit: v il (min) = -0.9v with a pulse width < 5 ns overshoot limit: v ih (max) = v dd q +0.9v with a pulse width < 5 ns v ih (dc) and v il (dc) are levels to maintain the current logic state. v ih (ac) and v il (ac) are levels to change to the new logic state.
w942508ch publication release date: may 21, 2003 - 9 - revision a3 7.3 capacitance (v dd = v ddq = 2.5v 0.2v, f = 1 mhz, t a = 25 c, v out (dc) = v ddq /2, v out (peak to peak) = 0.2v) symbol parameter min. max. delta (max.) unit c in input capacitance (except for clk pins) 2.0 3.0 0.5 pf c clk input capacitance (clk pins) 2.0 3.0 0.25 pf c i/o dq, dqs, dm capacit ance 4.0 5.0 0.5 pf c nc1 nc1 pin capacitance - 1.5 - pf c nc2 nc2 pin capacitance 4.0 5.0 - pf notes: these parameters are periodi cally sampled and not 100% tested. the nc2 pins have additional c apacitance for adjustment of t he adjacent pin capacitance. the nc2 pins have power and ground clamp. 7.4 leakage and output buffer characteristics symbol parameter min. max. units notes i i(l) input leakage current (0v < v in < v ddq , all other pins not under test = 0v) -2 2 a i o(l) output leakage current (output disabled, 0v < v out < v ddq ) -5 5 a v oh output high voltage (under ac test load condition) v tt +0.76 - v v ol output low voltage (under ac test load condition) - v tt -0.76 v i oh (dc) output minimum source dc current -15.2 - ma 4, 6 i ol (dc) output minimum sink dc current full strength 15.2 - ma 4, 6 i oh (dc) output minimum source dc current -10.4 - ma 5 i ol (dc) output minimum sink dc current half strength 10.4 - ma 5
w942508ch - 10 - 7.5 dc characteristics max. sym. parameter -5 -6 -7 -75 unit notes i dd0 operating current: one bank active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock c y cle 110 110 110 110 7 i dd1 operating current: one bank active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; i out = 0 ma; address and control inputs chan g in g once per clock c y cle. 120 120 120 120 7, 9 i dd2p precharge-power-down standby current: all banks idle; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm 8 8 8 8 i dd2f idle floating standby current: cs > v ih min; all banks idle; cke > v ih min; address and other control inputs changing once per clock cycle; vi n = vref for dq, dqs and dm 45 45 45 40 7 i dd2n idle standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other control inputs changing once per clock cycle; vin > v ih min or vin < v il max for dq, dqs and dm 45 45 45 40 7 i dd2q idle quiet standby current: cs > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other control inputs stable; vin > v ref for dq, dqs and dm 40 40 40 35 7 i dd3p active power-down sta ndby current: one bank active; power down mode; cke < v il max; t ck = t ck min 20 20 20 20 i dd3n active standby current: cs > v ih min; cke > v ih min; one bank active-precharge; t rc = t ras max; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and other control input s changing once per clock cycle 70 70 70 65 7 i dd4r operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock c y cle; cl=2.5; t ck = t ck min; i out = 0m a 165 165 165 155 7, 9 i dd4w operating current: burst = 2; write; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; dq, dm and dqs inputs chan g in g twice per clock c y cle 165 165 165 155 7 i dd5 auto refresh current: t rc = t rfc min 190 190 190 190 7 i dd6 self refresh current: cke < 0.2v 9 9 9 9 i dd7 random read current: 4 banks active read with activate every 20ns, auto-prec harge read every 20 ns; burst = 4; t rcd = 3; i out = 0ma; dq, dm and dqs inputs changing twice per clock c y cle; address chan g in g once per clock c y cle 270 270 270 270 ma ck ck dqs random read current timing t rcd t rc t ck = 10ns ( i dd7) bank 0 row d bank 3 row c bank 1 row e bank 1 row e address bank 0 row d bank 2 row f bank 3 row q bank 2 col f read ap act read ap command read ap act act read ap act dq qa qb qb qb qb qc qc qc qc qd qd qd qd qe qe qa bank 0 row h act bank 0 col d read ap act act act act bank 1 col e bank 2 row f bank 3 row q bank 2 col f bank 0 row h read ap bank 1 row e bank 3 col c bank 0 row d
w942508ch publication release date: may 21, 2003 - 11 - revision a3 7.6 ac characteristics and operating condition (notes: 10, 12) -7 -7 5 sym. parameter min. max. min. max. units notes t rc active to ref/active command period 65 65 t rfc ref to ref/active command period 75 75 t ras active to prechar g e command period 45 100000 45 100000 t rcd active to read/write command dela y time 20 20 t rap active to read with auto prechar g e enable 15 15 ns t ccd read/write ( a ) to read/write ( b ) command period 1 1 t ck t rp prechar g e to active command period 20 20 t rrd active ( a ) to active ( b ) command period 15 15 t wr write recover y time 15 15 t dal auto prechar g e write recover y + prechar g e time 30 30 cl = 2 7.5 15 8 15 t ck clk cycle time cl = 2.5 7 15 7.5 15 t ac data access time from clk, clk -0.75 0.75 -0.75 0.75 t dqsck dqs output access time from clk, clk -0.75 0.75 -0.75 0.75 16 t dqsq data strobe ed g e to out p ut data ed g e skew 0.5 0.5 ns t ch clk hi g h level width 0.45 0.55 0.45 0.55 t cl clk low level width 0.45 0.55 0.45 0.55 t ck 11 t hp clk half period (minimum of actual t ch, t cl ) min. ( t cl ,t ch ) min. ( t cl ,t ch ) t qh dq output data hold time from dqs t hp -0.75 t hp -0.75 ns t rpre dqs read preamble time 0.9 1.1 0.9 1.1 t rpst dqs read postamble time 0.4 0.6 0.4 0.6 t ck 11 t ds dq and dm setu p time 0.5 0.5 t dh dq and dm hold time 0.5 0.5 t dipw dq and dm in p ut pulse width ( for each in p ut ) 1.75 1.75 ns t dqsh dqs in p ut hi g h pulse width 0.35 0.35 t dqsl dqs in p ut low pulse width 0.35 0.35 t dss dqs fallin g ed g e to clk setu p time 0.2 0.2 t dsh dqs fallin g ed g e hold time from clk 0.2 0.2 t ck 11 t wpres clock to dqs write preamble set-u p time 0 0 ns t wpre dqs write preamble time 0.25 0.25 t wpst dqs write postamble time 0.4 0.4 t dqss write command to first dqs latchin g transition 0.75 1.25 0.75 1.25 11 t dssk udqs ? ldqs skew ( x 16 ) -0.25 0.25 -0.25 0.25 t ck t is in p ut setu p time 0.9 0.9 t ih in p ut hold time 0.9 0.9 t ipw control & address in p ut pulse width ( for each in p ut ) 2.2 2.2 t hz data-out high-impedance time from clk, clk -0.75 0.75 -0.75 0.75 t lz data-out low-impedance time from clk, clk -0.75 0.75 -0.75 0.75 t t(ss) sstl in p ut transition 0.5 1.5 0.5 1.5 ns t wtr internal write to read command dela y 11 t ck t xsnr exit self refresh to non-read command 75 75 ns t xsrd exit self refresh to read command 10 10 t ck t ref refresh time ( 8k ) 64 64 ms t mrd mode re g ister set c y cle time 15 15 ns
w942508ch - 12 - -5 -6 sym. parameter min. max. min. max. units notes t rc active to ref/active command period 55 60 t rfc ref to ref/active command period 70 72 t ras active to precharge command period 40 70000 42 100000 t rcd active to read/write command delay time 15 18 t rap active to read with auto precharge enable 15 15 ns t ccd read/write(a) to read/write(b) command period 1 1 t ck t rp precharge to active command period 15 18 t rrd active(a) to active(b) command period 10 12 t wr write recovery time 15 15 t dal auto precharge write recovery + precharge time 30 30 2.5 5 10 6 12 t ck clk cycle time 3 5 10 6 12 t ac data access time from clk, clk -0.7 0.7 -0.7 0.7 t dqsck dqs output access time from clk, clk -0.55 0.55 -0.6 0.6 16 t dqsq data strobe edge to output data edge skew 0.4 0.45 ns t ch clk high level width 0.45 0.55 0.45 0.55 t cl clk low level width 0.45 0.55 0.45 0.55 t ck 11 t hp clk half period (minimum of actual t ch, t cl ) min (t cl ,t ch ) min, (t cl ,t ch ) t qh dq output data hold time from dqs t hp -0.5 t hp -0.55 ns t rpre dqs read preamble time 0.9 1.1 0.9 1.1 t rpst dqs read postamble time 0.4 0.6 0.4 0.6 t ck 11 t ds dq and dm setup time 0.4 0.45 t dh dq and dm hold time 0.4 0.45 t dipw dq and dm input pulse width (for each input) 1.75 1.75 ns t dqsh dqs input high pulse width 0.35 0.35 t dqsl dqs input low pulse width 0.35 0.35 t dss dqs falling edge to clk setup time 0.2 0.2 t dsh dqs falling edge hold time from clk 0.2 0.2 t ck 11 t wpres clock to dqs write preamble set-up time 0 0 ns t wpre dqs write preamble time 0.25 0.25 t wpst dqs write postamble time 0.4 0.6 0.4 0.6 t dqss write command to first dqs latching transition 0.72 1.28 0.75 1.25 11 t dssk udqs ? ldqs skew (x 16) -0.25 0.25 -0.25 0.25 t ck t is input setup time 0.6 0.75 t ih input hold time 0.6 0.75 t ipw control & address input pulse width (for each input) 2.2 2.2 t hz data-out high-impedance time from clk, clk max t ac -0.7 0.7 t lz data-out low-impedance time from clk, clk -0.7 0.7 -0.7 0.7 t t(ss) sstl input transition 0.5 1.5 0.5 1.5 ns t wtr internal write to read command delay 2 2 t ck t xsnr exit self refresh to non-read command 75 75 ns t xsrd exit self refresh to read command 10 10 t ck t ref refresh time (8k) 64 64 ms t mrd mode register set cycle time 10 12 ns
w942508ch publication release date: may 21, 2003 - 13 - revision a3 7.7 ac test conditions parameter symbol value unit input high voltage (ac) v ih v ref +0.31 v input low voltage (ac) v il v ref -0.31 v input reference voltage v ref 0.5 x v ddq v termination voltage v tt 0.5 x v ddq v input signal peak to peak swing v swing 1.0 v differential clock input reference voltage v r v x (ac) v input difference voltage. clk and clk inputs (ac) v id (ac) 1.5 v input signal minimum slew rate slew 1.0 v/ns output timing measurement reference voltage v otr 0.5 x v ddq v v swing (max) v dd q v ss t t v ih min (ac) v ref v il max (ac) slew = (v ih min (ac) - v il max (ac)) / t output r t = 50 ohms vtt a.c. test load (a) z = 50 ohms output 30pf measurement point notes: (1) conditions outside the limits listed under "absolute maximum ratings" may cause permanent damage to the device. (2) all voltages are referenced to v ss , v ssq.( 2.6v 0.1v for ddr400 ) (3) peak to peak ac noise on v ref may not exceed 2% v ref(dc). (4) v oh = 1.95v, v ol = 0.35v (5) v oh = 1.9v, v ol = 0.4v (6) the values of i oh (dc) is based on v ddq = 2.3v and v tt = 1.19v. the values of i ol (dc) is based on v ddq = 2.3v and v tt = 1.11v. (7) these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck and t rc .
w942508ch - 14 - (8) v tt is not applied directly to the device. v tt is a system supply for signal terminat ion resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . (9) these parameters depend on the output loading. s pecified values are obtained with the output open. (10) transition times are measured between v ih min.(ac) and v il max.(ac).transition (rise and fall) of input signals have a fixed slope. (11) if the result of nominal calculation with regard to t ck contains more than one decimal pl ace, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.75 t ck , t ck = 7.5 ns, 0.75 7.5 ns = 5.625 ns is rounded up to 5.6 ns.) (12) v x is the differential clock cross point voltage where input timing meas urement is referenced. (13) v id is magnitude of the difference between clk input level and clk input level. (14) v iso means {v ick (clk)+v ick ( clk )}/2. (15) refer to the figure below. clk clk v ss v ick v x v x v x v x v x v ick v ick v ick v id(ac) v id(ac) 0 v differential v iso v iso(min) v iso(max) v ss (16) t ac and t dqsck depend on the clock jitter. these timi ng are measured at stable clock.
w942508ch publication release date: may 21, 2003 - 15 - revision a3 8. operation mode the following table shows the operation commands. 8.1 simplified truth table sym. command device state cken-1 cken dm (4) bs0 bs1 a10 a12, a11, a9-a0 cs ras cas we act bank active idle (3) h x x v v v l l h h pre bank precharge any (3) h x x v l x l l h l prea precharge all any h x x x h x l l h l writ write active (3) h x x v l v l h l l writa write with auto precharge active (3) h x x v h v l h l l read read active (3) h x x v l v l h l h reada read with auto precharge active (3) h x x v h v l h l h mrs mode register set idle h x x l, l c c l l l l emrs extended mode regiser set idle h x x h, l v v l l l l nop no operation any h x x x x x l h h h bst burst read stop active h x x x x x l h h l dsl device deselect any h x x x x x h x x x aref auto refresh idle h h x x x x l l l h self self refresh entry idle h l x x x x l l l h h x x x selex self refresh exit idle (self refresh) l h x x x x l h h x h x x x pd power down mode entry idle/ active (5) h l x x x x l h h x h x x x pdex power down mode exit any (power down) l h x x x x l h h x wde data write enable active h x l x x x x x x x wdd data write disable active h x h x x x x x x x notes : 1. v = valid x = don?t care l = low level h = high level 2. cke n signal is input level when commands are issued. cke n-1 signal is input level one clock cy cle before the commands are issued. 3. these are state designated by the bs0, bs1 signals. 4. ldm, udm (w942516ch) 5. power down mode can not entry in the burst cycle.
w942508ch - 16 - 8.2 function truth table (note 1) current state cs ras cas we address command action notes h x x x x dsl nop l h h x x nop/bst nop l h l h bs, ca, a10 read/reada illegal 3 l h l l bs, ca, a10 writ/writa illegal 3 l l h h bs, ra act row activating l l h l bs, a10 pre/prea nop l l l h x aref/self refresh or self refresh 2 idle l l l l op-code mrs/emrs mode register accessing 2 h x x x x dsl nop l h h x x nop/bst nop l h l h bs, ca, a10 read/reada begin read: determine ap 4 l h l l bs, ca, a10 writ/writa begin write: determine ap 4 l l h h bs, ra act illegal 3 l l h l bs, a10 pre/prea precharge 5 l l l h x aref/self illegal row active l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst burst stop l h l h bs, ca, a10 read/reada term burst, new read: determine ap 6 l h l l bs, ca, a10 writ/writa illegal l l h h bs, ra act illegal 3 l l h l bs, a10 pre/prea term burst, precharging l l l h x aref/self illegal read l l l l op-code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h bs, ca, a10 read/reada term burst, start read: determine ap 6, 7 l h l l bs, ca, a10 writ/writa term burst, start read: determine ap 6 l l h h bs, ra act illegal 3 l l h l bs, a10 pre/prea term burst. precharging 8 l l l h x aref/self illegal write l l l l op-code mrs/emrs illegal
w942508ch publication release date: may 21, 2003 - 17 - revision a3 function truth table, continued current state cs ras cas we address command action notes h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h bs, ca, a10 read/read a illegal l h l l bs, ca, a10 writ/writ a illegal 3 l l h h bs, r a act illegal 3 l l h l bs, a10 pre/pre a illegal l l l h x aref/self illegal read with auto prechange l l l l o p -code mrs/emrs illegal h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h bs, ca, a10 read/read a illegal l h l l bs, ca, a10 writ/writ a illegal l l h h bs, r a act illegal 3 l l h l bs, a10 pre/pre a illegal 3 l l l h x aref/self illegal write with auto precharge l l l l o p -code mrs/emrs illegal h x x x x dsl nop -> idle after t rp l h h h x nop no p -> idle after t rp l h h l x bst illegal l h l h bs, ca, a10 read/read a illegal 3 l h l l bs, ca, a10 writ/writ a illegal 3 l l h h bs, r a act illegal 3 l l h l bs, a10 pre/pre a no p ->idle after t rp l l l h x aref/self illegal precharging l l l l o p -code mrs/emrs illegal h x x x x dsl nop -> row active after l h h h x nop no p -> row active after l h h l x bst illegal l h l h bs, ca, a10 read/read a illegal 3 l h l l bs, ca, a10 writ/writ a illegal 3 l l h h bs, r a act illeg a l3 l l h l bs, a10 pre/pre a illegal 3 l l l h x aref/self illegal row activating l l l l o p -code mrs/emrs illegal
w942508ch - 18 - function truth table, continued current state cs ras cas we address command action notes h x x x x dsl nop -> row active after t wr l h h h x nop no p -> row active after t wr l h h l x bst illegal l h l h bs, ca, a10 read/read a illegal 3 l h l l bs, ca, a10 writ/writ a illegal 3 l l h h bs, r a act illegal 3 l l h l bs, a10 pre/pre a illegal 3 l l l h x aref/self illegal write recovering l l l l o p -code mrs/emrs illegal h x x x x dsl nop -> enter precharge after t wr l h h h x nop no p -> enter p rechar g e after t wr l h h l x bst illegal l h l h bs, ca, a10 read/read a illegal 3 l h l l bs, ca, a10 writ/writ a illegal 3 l l h h bs, r a act illegal 3 l l h l bs, a10 pre/pre a illegal 3 l l l h x aref/self illegal write recovering with auto precharge l l l l o p -code mrs/emrs illegal h x x x x dsl nop -> idle after t rc l h h h x nop no p -> idle after t rc l h h l x bst illegal l h l h x read/writ illegal l l h x x act/pre/pre a illegal refreshing l l l x x aref/self/mrs/em illegal h x x x x dsl nop -> row after t mrd l h h h x nop no p -> row after t mrd l h h l x bst illegal l h l x x read/writ illegal mode register accessing l l x x x act/pre/prea/are f /s elf / mr s/ emr s illegal notes : 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle. 2. illegal if any bank is not idle. 3. illegal to bank in specified states; function may be legal in t he bank indicated by bank address (bs), depending on the state of that bank. 4. illegal if t rcd is not satisfied. 5. illegal if t ras is not satisfied. 6. must satisfy burst interrupt condition. 7. must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. must mask preceding data which don?t satisfy t wr remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data
w942508ch publication release date: may 21, 2003 - 19 - revision a3 8.3 function truth table for cke cke current state n-1 n cs ras cas we address action notes h x x x x x x invalid l h h x x x x exit self refresh -> idle after t xsnr l h l h h x x exit self refresh -> idle after t xsnr l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x maintain self refresh h x x x x x x invalid l h x x x x x exit power down -> idle after t is power down l l x x x x x maintain power down mode h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h x x enter power down 2 h l l l l h x self refresh 1 h l l h l x x illegal h l l l x x x illegal all banks idle l x x x x x x power down 2 h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h x x enter power down 2 h l l l l h x illegal h l l h l x x illegal h l l l x x x illegal row active l x x x x x x power down any state other than listed above h h x x x x x refer to function truth table notes : 1. self refresh can enter only from the all banks idle state. 2. power down can enter only from bank idle or row active state. remark: h = high level, l = low level, x = high or low level (don?t care), v = valid data
w942508ch - 20 - 8.4 simplified state diagram power applied automatic sequence command sequence read a write read row active power down idle mode register set auto refresh self refresh read read a write write a pre charge power on mrs/emrs aref sref srefx pd pdex act bst read write write a write a read a pre pre pre pre active powerdown pd pdex read read a
w942508ch publication release date: may 21, 2003 - 21 - revision a3 9. functional description 9.1 power up sequence (1) apply power and attempt to cke at a low state ( s (min.). (3) after stable power and clock, apply nop and take cke high. (4) issue emrs (extended mode register set) to enable dll and establish output driver type. (5) issue mrs (mode register set) to rese t dll and set device to idle with bit a8. (an additional 200 cycles(min) of clock are required for dll lock) (6) issue precharge command for all banks of the device. (7) issue two or more auto refresh commands. (8) issue mrs-initialize device operation. (if device operation mode is set at sequence 5, sequence 8 can be skipped.) 9.2 command function 1. bank activate command ( ras = "l", cas = "h", we = "h", bs0, bs1 = bank, a0 to a12 = row address) the bank activate command activates the ban k designated by the bs (b ank address) signal. row addresses are latched on a0 to a12 when this command is issued and the cell data is read out of the sense amplifiers. the maximum time t hat each bank can be held in the active state is specified as t ras (max) . after this command is issued, read or write operation can be executed. 2. bank precharge command ( ras = "l", cas = "h", we = "l", bs0, bs1 = bank, a10 = "l", a0 to a9, a11, a12 = don?t care) the bank precharge command percharges the bank designated by bs. the precharged bank is switched from the active state to the idle state. 3. precharge all command ( ras = "l", cas = "h", we = "l", bs0, bs1 = don?t care, a10 = "h", a0 to a9, a11, a12 = don?t care) the precharge all command precharges all bank s simultaneously. then all banks are switched to the idle state. 4. write command ( ras = "h", cas = "l", we = "l", bs0, bs1 = bank, a10 = "l", a0 to a9, a11 = column address)
w942508ch - 22 - the write command performs a write operation to the bank designated by bs. the write data are latched at both edges of dqs. the length of the write data (burst length) and column access sequence (addressing mode) must be in the mode register at power-up prior to the write operation. 5. write with auto precharge command ( ras ="h", cas = "l", we = "l", bs0, bs1 = bank, a10= "h", a0 to a9, a11 = column address) the write with auto precharge command performs the precharge operation automatically after the write operation. this command must not be interrupted by any other commands. 6. read command ( ras ="h", cas = "l", we = "h", bs0, bs1 = bank, a10 = "l", a0 to a9, a11 = column address) the read command performs a read operation to the bank designated by bs. the read data are synchronized with both edges of dqs. the l ength of read data (burst length), addressing mode and cas latency (access time from cas command in a clock cycle) must be programmed in the mode register at power-up prior to the read operation. 7. read with auto precharge command ( ras = "h", cas = "l", we = "h", bs0, bs1 = bank, a10 = "h", a0 to a9, a11 = column address) the read with auto precharge command automatically performs the precharge operation after the read operation. 1) reada t ras (min) - (bl/2) x t ck internal precharge operation begins after bl /2 cycle from read with auto precharge command. 2) t rcd(min) reada < t ras(min) - (bl/2) x t ck data can be read with shortest latency, but the internal precharge operation does not begin until after t ras (min) has completed. this command must not be interrupted by any other command. 8. mode register set command ( ras = "l", cas = "l", we = "l", bs0 = "l", bs1 = "l", a0 to a12 = register data) the mode register set command programs the values of cas latency, addressing mode, burst length and dll reset in the mode register. the default values in the mode register after power-up are undefined, therefore this command must be issued during the power-up sequence. also, this command can be issued while all banks are in the idle state. refer to the table for specific codes.
w942508ch publication release date: may 21, 2003 - 23 - revision a3 9. extended mode register set command ( ras = "l", cas = "l", we = "l", bs0 = "h", bs1 = "l", a0 to a12 = register data) the extended mode register set command can be implemented as needed for function extensions to the standard (sdr -sdram). currently the only available mode in emrs is dll enable/disable, decoded by a0. the default value of the extended mode register is not defined; therefore this command must be issued during t he power-up sequence for enabling dll. refer to the table for specific codes. 10. no-operation command ( ras = "h", cas = "h", we = "h") the no-operation command simply performs no operation (same command as device deselect). 11. burst read stop command ( ras = "h", cas = "h", we = "l") the burst stop command is used to stop the burst operation. this command is only valid during a burst read operation. 12. device deselect command ( cs = "h") the device deselect command disabl es the command decoder so that the ras , cas , we and address inputs are ignored. this command is similar to the no-operation command. 13. auto refresh command ( ras = "l", cas = "l", we = "h", cke = "l", bs0, bs1, a0 to a12 = don?t care) the auto refresh command is used to refresh the row address provided by the internal refresh counter. the refresh operation must be perfo rmed 8192 times within 64ms. the next command can be issued after t ref from the end of the auto refres h command. when the auto refresh command is used, all banks must be in the idle state. 14. self refresh entry command ( ras = "l", cas = "l", we = "h", cke = "l", bs0, bs1, a0 to a12 = don?t care) the self refresh entry command is used to enter se lf refresh mode. while the device is in self refresh mode, all input and output buffer (except the cke buffer) are disabled and the refresh operation is automatically performed. self refres h mode is exited by taking cke "high" (the self refresh exit command). during self refresh, dlll is disable. 15. self refresh exit command (cke = "h", cs = "h" or cke = "h", ras = "h", cas = "h") this command is used to exit from self refresh mode. any subsequent commands can be issued after t xsnr (t xsrd for read command) from the end of this command.
w942508ch - 24 - 16. data write enable /disable command (dm = "l/h" or ldm, udm = "l/h") during a write cycle, the dm or ldm, udm signal functions as data mask and can control every word of the input data. the ldm signal controls dq0 to dq7 and udm signal controls dq8 to dq15. 9.3 read operation issuing the bank activate command to the idle bank puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized with both edges of dq s (burst read operation). the in itial read data becomes available after cas latency from the issuing of the read command. the cas latency must be set in the mode register at power-up. when the precharge operation is performed on a bank during a burst read and operation, the burst operation is terminated. when the read with auto precharge command is issued, the precharge operation is performed automatically after the read cycle, then the bank is switched to the id le state. this command cannot be interrupted by any other commands. re fer to the diagrams for read operation. 9.4 write operation issuing the write command after t rcd from the bank activate command. the input data is latched sequentially, synchronizing with both edges(rising &falling) of dqs after the write command (burst write operation). the burst length of the write data (burst length) and addressing mode must be set in the mode register at power-up. when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the write with auto precharge command is issued, the precharge operation is performed automatically after the write cycle, then the bank is switched to the idle state, the write with auto precharge command cannot be interrupted by any other command for the entire burst data duration. refer to the diagrams for write operation. 9.5 precharge there are two commands, which perform the precharge operation (bank precharge and precharge all). when the bank precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. the bank pr echarge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max) . therefore, each bank must be precharged within t ras(max) from the bank activate command. the precharge all command can be used to precha rge all banks simultaneously. even if banks are not in the active state, the precharge all command can still be issued. in this case, the precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state.
w942508ch publication release date: may 21, 2003 - 25 - revision a3 9.6 burst termination when the precharge command is used for a bank in a burst cycle, the burst operation is terminated. when burst read cycle is interrupted by the precharge command, read operation is disabled after clock cycle of ( cas latency) from the precharge command. w hen the burst write cycle is interrupted by the precharge command . the input circuit is rese t at the same clock cycl e at which the precharge command is issued. in this case, the dm signal must be asserted "high": during t wr to prevent writing the invalided data to the cell array. when the burst read stop command is issued for t he bank in a burst read cycle, the burst read operation is terminated. the burst read stop command is not supported during a write burst operation. refer to the diagrams for burst termination. 9.7 refresh operation two types of refresh operation can be performed on the device: auto refresh and self refresh. by repeating the auto refresh cycle, each bank in turn refreshed automatically. the refresh operation must be performed 8192 times(rows) within 64 ms. the period between the auto refresh command and the next command is specified by t rfc . self refresh mode enter issuing the self refresh command (cke asserted "low"). while all banks are in the idle state. the device is in self refresh m ode for as long as cke held "low". in the case of 8192 burst auto refresh commands, 8192 burst auto refresh commands must be performed within 7.8 s before entering and after exiting the self refresh m ode. in the case of di stributed auto refresh commands, distributed auto refresh commands must be issued every 7.8 s and the last distributed auto refresh commands must be performed within 7.8 s before entering the self refresh mode. after exiting from the self refresh mode, the refr esh operation must be performed within 7.8 s. in self refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except cke buffer). refer to the diagrams for refresh operation. 9.8 power down mode two types of power down mode can be performed on the device: active standby power down mode and precharge standby power down mode. when the device enters the power down mode, all input/output buffers and dll are disabled resulting in low power dissipation (except cke buffer). power down mode enter asserting cke "low" while the device is not running a burst cycle. taking cke: "high" can exit this mode. when cke goes hi gh, a no operation command must be input at next clk rising edge. refer to the diagrams for power down mode. 9.9 mode register operation the mode register is programmed by the mode register set command (mrs/emrs) when all banks are in the idle state. the data to be set in the m ode register is transferred using the a0 to a12 and bs0, bs1 address inputs. the mode register designates the operation mode fo r the read or write cycle. the register is divided into five filed: (1) burst length field to set the l ength of burst data (2) addressing mode selected bit to designate the column access sequence in a burst cycle (3) cas latency field to set the assess time in clock cycle (4) dll reset field to reset the d ll (5) regular/extended mode register filed to select a
w942508ch - 26 - type of mrs (regular/extended mrs) . emrs cycle can be implement ed the extended function (dll enable/disable mode) the initial value of the mode register (includi ng emrs) after power up is undefined; therefore the mode register set command must be issued before power operation. (1) burst length field (a2 to a0) this field specifies the data length for column ac cess using the a2 to a0 pins and sets the burst length to be 2, 4, and 8 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x reserved (2) addressing mode select (a3) the addressing mode can be one of two modes; interleave mode or sequential mode, when the a3 bit is "0", sequential mode is selected. when the a3 bit is "1", interleave mode is selected. both addressing mode support burst length 2, 4, and 8 words. a3 addressing mode 0 sequential 0 interleave
w942508ch publication release date: may 21, 2003 - 27 - revision a3 ? address sequence of sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst length as the following. addressing sequence of sequential mode data access address burst length data 0 n 2 words (address bits is a0) data 1 n + 1 not carried from a0 to a1 data 2 n + 2 4 words (address bit a0, a1) data 3 n + 3 not carried from a1 to a2 data 4 n + 4 data 5 n + 5 8 words (address bits a2, a1 and a0) data 6 n + 6 not carried from a2 to a3 data 7 n + 7 ? addressing sequence of interleave mode a column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. 9.9.1.1 address sequence for interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 4 words data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 8 words data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
w942508ch - 28 - (3) cas latency field (a6 to a4) this field specifies the number of clock cycles from the assertion of the read command to the first data read. the minimum values of cas latency depends on the frequency of clk. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved (4) dll reset bit (a8) this bit is used to reset dll. when the a8 bit is "1", dll is reset. (5) mode register /extended mode register change bits (bs0, bs1) these bits are used to select mrs/emrs. bs1 bs0 a12-a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1 x reserved (6) extended mode register field 1) dll switch field (a0) this bit is used to select dll enable or disable a0 dll 0 enable 1 disable 2) output driver size control field (a1) this bit is used to select output driver size, both full strength and half strength are based on jedec standard. a1 output driver 0 full strength 1 half strength (7) reserved field ? test mode entry bit (a7) this bit is used to enter test mode and must be set to "0" for normal operation. ? reserved bits (a9, a10, a11, a12) these bits are reserved for future operations. they must be set to "0" for normal operation.
w942508ch publication release date: may 21, 2003 - 29 - revision a3 10. timing waveforms 10.1 command input timing clk clk t ck t ck t cl t ch t is t ih t is t ih t is t ih t is t ih t is t ih cs ras cas we a0~a12 bs0, 1 refer to the command truth table 10.2 timing of the clk signals t ck t t t t v ih v ih(ac) v il(ac) v il clk clk clk clk v x v x v x v ih v il t ch t cl
w942508ch - 30 - timing waveforms, continued 10.3 read timing (burst length = 4) t is t ih da0 da1 da2 t ch t cl t ck add cmd clk clk read col qa0 qa1 qa2 da3 qa3 t rpre t dqsck t dqsck t dqsck t rpst postamble preamble hi-z hi-z t dqsq t dqsq t dqsq t qh t qh t ac t lz t hz hi-z hi-z da0 da1 da2 qa0 qa1 qa2 da3 qa3 t rpe t dqsck t dqsck t dqsck t rpst postamble preamble hi-z hi-z t dqsq t dqsq t dqsq t qh t qh t ac t lz t hz hi-z hi-z cas dqs output (data) latency=2 cas dqs output (data) latency=2.5 note: the correspondence of ldqs, udqs to dq. ( w942516ah) ldqs dq0~7 dq8~15 udqs t is t ih
w942508ch publication release date: may 21, 2003 - 31 - revision a3 timing waveforms, continued 10.4 write timing (burst length = 4) t is t ih tdsh t dss t dss t dsh t wpres t dh t dh t dh t ds t ds t ds t dqss t dsh t dsh t dss t dss postamble t wpre preamble tdqsh tdqsh tdqsl twpst da0 da1 da2 da3 t wpres t dh t dh t dh t ds t ds t ds t dqss t dsh t dsh t dss t dss postamble t wpre preamble t dqsh t dqsh t dqsl t wpst da0 da1 da2 da3 t wpres t dh t ds t ds t dqss t dsh postamble t wpre preamble t dqsh t dqsh t dqsl t wpst da0 da1 da2 da3 t dssk t dssk t dssk t dssk t ds t dh t dh t ch t cl t ck dqs input (data) ldqs dq0~7 udqs dq8~15 x4, x8 device x16 device add cmd clk clk writ col da0 da1 da2 da3 da3 da2 da1 da0 da0 da1 da2 da3 note: x16 has 2dqs?s (udqs for uper byte and ldqs for lower byte). even if one of the 2 bytes is not used, both udqs and ldqs must be toggled.
w942508ch - 32 - timing waveforms, continued 10.5 dm, data mask (w942508ch/w942504ch) writ t dipw t dipw t dh t dh t ds t ds masked /clk clk cmd dqs dm dq d3 d1 d0 10.6 dm, data mask (w942516ch ) writ t dipw t dipw t dh t dh t ds t ds masked /clk clk cmd ldqs ldm dq0~ dq7 d3 d1 d0 t dipw t dipw t dh t dh t ds t ds masked udqs udm dq8~ dq15 d3 d2 d0
w942508ch publication release date: may 21, 2003 - 33 - revision a3 timing waveforms, continued 10.7 mode register set (mrs) timing mrs register set data next cmd t mrd clk clk cmd add a2 a1 a0 a3 a6 a5 a4 a8 bs1 bs0 000 000 001 010 011 100 101 110 111 001 010 011 100 101 110 111 0 1 0 1 1 1 0 0 0 1 0 1 2 4 8 2 4 8 burst length sequential interleaved reserved reserved reserved reserved reserved reserved sequential interleaved addressing mode cas latency 2 dll reset no yes mrs or emrs regular mrs cycle extended mrs cycle 2.5 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 bs0 bs1 "0" "0" "0" "0" "0" "0" "0" dll reset reserved addressing mode * "reserved" should stay "0" during mrs cycle. reserved mode register set or extended mode register set cas latency burst length reserved reserved 3
w942508ch - 34 - timing waveforms, continued 10.8 extend mode register set (emrs) timing emrs register set data next cmd t mrd clk clk cmd add a0 a1 bs1 bs0 0 1 0 1 1 1 0 0 0 1 0 1 enable disable dll switch output driver size full strength hall strength mrs or emrs regular mrs cycle extended mrs cycle a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 bs0 bs1 "0" "0" "0" "0" "0" "0" "0" * "reserved" should stay "0" during emrs cycle. "0" "0" "0" "0" "0" "0" output driver dll switch reserved mode register set or extended mode register set
w942508ch publication release date: may 21, 2003 - 35 - revision a3 timing waveforms, continued 10.9 auto precharge timing (read cycle, cl = 2) 1) trcd (reada) tras (min) ? (bl/2) tck ap q7 q6 q5 q4 q3 q2 q1 q0 act reada act q0 q1 q2 q3 act reada act q0 q1 act ap reada act trp t ras cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap notes: cl2 shown; same command operation timing with cl = 2.5 in this case , the internal precharge operati on begin after bl/2 cycle from reada command. ap represents the start of internal precharging . the read with auto precharge command cannot be interrupted by any other command.
w942508ch - 36 - timing waveforms, continued 2) trcd/rap(min) trcd (reada) < tras (min) ? (bl/2) tck ap q7 q6 q5 q4 q3 q2 q1 q0 act reada act q0 q1 q2 q3 act reada act q0 q1 act ap reada act t rp t ras cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap t rap t rcd t rap t rcd t rap t rcd notes: cl2 shown; same command operation timing with cl = 2.5 in this case , the internal precharge operation does not begin until after t ras (min) has command. ap represents the start of internal precharging . the read with auto precharge command cannot be interrupted by any other command.
w942508ch publication release date: may 21, 2003 - 37 - revision a3 timing waveforms, continued 10.10 auto precharge timing (write cycle) ap writa act act writa act writa cmd dqs dq cmd dqs dq cmd dqs dq bl=2 bl=4 bl=8 clk clk ap ap d0 d1 d0 d1 d2 d3 d0 d1 d2 d3 d4 d5 d6 d7 t dal t dal t dal the write with auto precharge command cannot be interrupted by any other command. ap represents the start of internal precharging .
w942508ch - 38 - timing waveforms, continued 10.11 read interrupted by read (cl = 2, bl = 2, 4, 8) cmd add dqs clk clk dq act read a read b read c read d read e row address col,add,a col,add,b col,add,c col,add,d col,add,e qc0 qa0 qa1 qb0 qb1 t ccd t ccd t ccd t ccd t rcd 10.12 burst read stop (bl = 8) read cmd dqs dq clk clk bst q0 q1 q2 q3 q4 q5 q0 q1 q2 q3 q4 q5 cas latency cas latency cas latency=2 dqs dq cas latency=2.5
w942508ch publication release date: may 21, 2003 - 39 - revision a3 timing waveforms, continued 10.13 read interrupted by write & bst (bl = 8) read cmd dqs dq clk clk bst q0 q1 q2 q3 q4 q5 cas latency=2 writ d0 d1 d2 d3 d4 d5 d6 d7 read cmd dqs dq bst q0 q1 q2 q3 q4 q5 cas latency=2.5 writ d0 d1 d2 d3 d4 d5 d6 d7 burst read cycle must be terminated by bst command to avoid i/o conflict. 10.14 read interrupted by precharge (bl = 8) read cmd dqs dq clk clk pre q0 q1 q2 q3 q4 q5 q0 q1 q2 q3 q4 q5 cas latency cas latency cas latency=2 dqs dq cas latency=2.5
w942508ch - 40 - timing waveforms, continued 10.15 write interrupted by write (bl = 2, 4, 8) cmd add dqs clk clk dq act writ a writ b writ c writ d writ e row address col. add. a col.add.b col. add. c col. add. d col. add. e dc0 dc1 dd0 dd1 da0 da1 db0 db1 t ccd t ccd t ccd t ccd t rcd 10.16 write interrupted by read (cl = 2, bl = 8) writ cmd dqs dm clk clk t wtr dq d4 d5 d6 d7 d0 d1 d2 d3 data must be masked by dm read data masked by read command, dqs input ignored. q4 q5 q6 q7 q0 q1 q2 q3
w942508ch publication release date: may 21, 2003 - 41 - revision a3 timing waveforms, continued 10.17 write interrupted by read (cl = 2.5, bl = 4) writ cmd dqs dm clk clk read t wtr dq q0 q1 q2 q3 d0 d1 d2 d3 data must be masked by dm 10.18 write interrupted by precharge (bl = 8) writ cmd dqs dm clk clk act t wr dq d4 d5 d6 d7 d0 d1 d2 d3 data must be masked by dm pre t rp data masked by pre command, dqs input ignored.
w942508ch - 42 - timing waveforms, continued 10.19 2 bank interleave read operation (cl = 2, bl = 2) ? tck = 100 mhz cmd dqs clk clk dq q0a q1a q0b q1b acta/b : bank act. cmd of bank a/b readaa/b : read with auto pre.cmd of bank a/b apa/b : auto pre. of bank a/b acta actb readaa acta readab actb apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) t rp(b) cl(a) cl(b) preamble postamble preamble postamble t rrd t rc(a) t rc(b) t rrd 10.20 2 bank interleave read operation (cl = 2, bl = 4) cmd dqs clk clk dq q2a q3a q2b q3b acta/b : bank act. cmd of bank a/b readaa/b : read with auto pre.cmd of bank a/b apa/b : auto pre. of bank a/b acta readaa actb readab acta actb apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) t rp(b) cl(a) cl(b) preamble postamble t rrd t rc(a) t rc(b) t rrd q0a q1a q0b q1b
w942508ch publication release date: may 21, 2003 - 43 - revision a3 timing waveforms, continued 10.21 4 bank interleave read operation (cl = 2, bl = 2) cmd dqs clk clk dq q0a q1a q0b q1b acta/b/c/d : bank act. cmd of bank a/b/c/d readaa/b/c/d : read with auto pre.cmd of bank a/b/c/d apa/b/c/d : auto pre. of bank a/b/c/d acta actb readaa actc readab actd readac acta apa apb t rcd(a) t ras(a) t rp t ras(b) t rcd(b) cl(a) cl(b) preamble postamble preamble t rrd t rc(a) t rrd t ras(c) t ras(d) t rcd(d) t rcd(c) t rrd t rrd 10.22 4 bank interleave read operation (cl = 2, bl = 4) cmd dqs clk clk dq acta/b/c/d : bank act. cmd of bank a/b/c/d readaa/b/c/d : read with auto pre.cmd of bank a/b/c/d apa/b/c/d : auto pre. of bank a/b/c/d acta readaa actb readab actc readac actd readad acta apa apb t rcd(a) t ras(a) t rp(a) t ras(b) t rcd(b) cl(a) cl(b) t rrd t rc(a) t rrd t ras(c) t ras(d) t rcd(d) t rcd(c) t rrd t rrd q2a q3a q2b q3b cl(c) preamble q0a q1a q0b q1b q0a q1a cl(b) cl(b) apc
w942508ch - 44 - timing waveforms, continued 10.23 auto refresh cycle cmd clk clk prea aref aref cmd nop nop nop t rp t rfc t rfc cke has to be kept "high" level for auto-refresh cycle. 10.24 active power down mode entry and exit timing cmd clk clk nop cmd nop exit entry nop nop t ih t is t ck t ih t is cke 10.25 precharged power down mode entry and exit timing cmd clk clk nop cmd nop exit entry nop nop t ih t is t ck t ih t is cke
w942508ch publication release date: may 21, 2003 - 45 - revision a3 timing waveforms, continued 10.26 self refresh entry and exit timing cmd clk clk t ih t is t ck t ih t is self cmd selfx nop nop prea exit entry cke t rp t xsrd nop self t xsnr selfx nop act read nop exit entry
w942508ch - 46 - 11. package dimension 11.1 tsop 66l ? 400 mil
w942508ch publication release date: may 21, 2003 - 47 - revision a3 12. revision history revision date page description aug. 28, 2002 - preliminary datasheet jan. 9, 2003 28 add cas latency = 3 option a1 feb. 14, 2003 - modified ac timing spec. a2 feb. 14, 2003 10 change i dd 2p current to 8 ma change i dd 6 current to 9 ma a3 may 21, 2003 add cl2.5 optional in ddr400 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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